1032 search results - page 107 / 207 » Extended Computation Tree Logic |
FTCS
1994
14 years 11 months ago
1994
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
FOSSACS
2007
Springer
15 years 4 months ago
2007
Springer
We study the complexity of satisfiability for the expressive extension ICPDL of PDL (Propositional Dynamic Logic), which admits intersection and converse as program operations. Ou...
LICS
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper describes an assembly-language type system capable of ensuring memory safety in the presence of both heap and stack allocation. The type system uses linear logic and a ...
ICTAC
2004
Springer
15 years 3 months ago
2004
Springer
We present a spatial and temporal logic based on Duration Calculus for the specification and verification of mobile real-time systems. We demonstrate the use of the formalism and...
ARITH
2003
IEEE
15 years 3 months ago
2003
IEEE
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...