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» Extending Reflective Architectures
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DATE
2005
IEEE
113views Hardware» more  DATE 2005»
15 years 10 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
RTAS
1997
IEEE
15 years 8 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
ICDE
1995
IEEE
180views Database» more  ICDE 1995»
16 years 5 months ago
Building an Integrated Active OODBMS: Requirements, Architecture, and Design Decisions
Active OODBMSs must provide e cient support for event detection, composition, and rule execution. Previous experience, reported here, building active capabilities on top of existi...
Alejandro P. Buchmann, Jürgen Zimmermann, Jos...
ASPLOS
2010
ACM
15 years 10 months ago
Cortical architectures on a GPGPU
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
Andrew Nere, Mikko Lipasti
ANCS
2006
ACM
15 years 10 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...