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ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
15 years 2 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
HPCA
1999
IEEE
15 years 2 months ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
CIKM
1999
Springer
15 years 2 months ago
A Comparison of Alternative Continuous Display Techniques with Heterogeneous Multi-Zone Disks
A number of recent technological trends have made data intensive applications such as continuous media audio and video servers a reality. These servers are expected to play an i...
Shahram Ghandeharizadeh, Seon Ho Kim
108
Voted
CONCUR
1999
Springer
15 years 2 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 2 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald