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ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 9 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
CASES
2007
ACM
15 years 9 months ago
A self-maintained memory module supporting DMM
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challeng...
Weixing Ji, Feng Shi, Baojun Qiao
NETWORKING
2007
15 years 6 months ago
Accelerated Packet Placement Architecture for Parallel Shared Memory Routers
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...
Brad Matthews, Itamar Elhanany, Vahid Tabatabaee
DEBU
2010
113views more  DEBU 2010»
15 years 2 months ago
Storage Class Memory Aware Data Management
Storage Class Memory (SCM) is here to stay. It has characteristics that place it in a class apart both from main memory and hard disk drives. Software and systems, architectures a...
Bishwaranjan Bhattacharjee, Mustafa Canim, Christi...
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ICDE
1999
IEEE
150views Database» more  ICDE 1999»
16 years 6 months ago
Managing Distributed Memory to Meet Multiclass Workload Response Time Goals
In this paper we present an online method for managing a goaloriented buffer partitioning in the distributed memory of a network of workstations. Our algorithm implements a feedba...
Arnd Christian König, Markus Sinnwell