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IPPS
2002
IEEE
15 years 11 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
ISCA
1992
IEEE
111views Hardware» more  ISCA 1992»
15 years 10 months ago
Lazy Release Consistency for Software Distributed Shared Memory
Relaxed memory consistency models, such as release consistency, were introduced in order to reduce the impact of remote memory access latency in both software and hardware distrib...
Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
15 years 9 months ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
STTT
2010
115views more  STTT 2010»
15 years 4 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
ICPP
2007
IEEE
16 years 14 days ago
Architectural Challenges in Memory-Intensive, Real-Time Image Forming
The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial quest...
Anders Ahlander, H. Hellsten, K. Lind, J. Lindgren...