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ASPLOS
2011
ACM
14 years 10 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
ARC
2010
Springer
387views Hardware» more  ARC 2010»
16 years 1 months ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides
IEEEARES
2008
IEEE
16 years 24 days ago
Type and Effect Annotations for Safe Memory Access in C
In this paper, we present a novel type and effect analysis for detecting memory errors in C source code. We extend the standard C type system with effect, region, and host annotat...
Syrine Tlili, Mourad Debbabi
ICPP
2006
IEEE
16 years 13 days ago
Parallel Information Extraction on Shared Memory Multi-processor System
Text Mining is one of the best solutions for today and the future’s information explosion. With the development of modern processor technologies, it will be a mass market deskto...
Jiulong Shan, Yurong Chen, Qian Diao, Yimin Zhang
IPPS
2006
IEEE
16 years 13 days ago
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
Currently run-time reconfigurable hardware offers really attractive features for embedded systems, such as flexibility, reusability, high performance and, in some cases, low-power...
Elena Perez Ramo, Javier Resano, Daniel Mozos, Fra...