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CODES
2007
IEEE
15 years 8 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
ICIP
1999
IEEE
16 years 4 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
TVLSI
2002
102views more  TVLSI 2002»
15 years 2 months ago
Power-optimal encoding for a DRAM address bus
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
Wei-Chung Cheng, Massoud Pedram
105
Voted
SSDBM
2007
IEEE
116views Database» more  SSDBM 2007»
15 years 8 months ago
A Distributed Algorithm for Joins in Sensor Networks
Given their autonomy, flexibility and large range of functionality, wireless sensor networks can be used as an effective and discrete means for monitoring data in many domains. T...
Alexandru Coman, Mario A. Nascimento
133
Voted
ICESS
2007
Springer
15 years 8 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam