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FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
15 years 6 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
15 years 6 months ago
Scalable performance scheduling for hardware-software cosynthesis
The paper presents a static process schedulingapproach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike ea...
Thomas Benner, Rolf Ernst, Achim Österling
JLP
2007
98views more  JLP 2007»
15 years 2 months ago
Tempus fugit: How to plug it
Secret or private information may be leaked to an external attacker through the timing behaviour of the system running the untrusted code. After introducing a formalisation of thi...
Alessandra Di Pierro, Chris Hankin, Igor Siveroni,...
FPL
2005
Springer
226views Hardware» more  FPL 2005»
15 years 8 months ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...
WDAG
2004
Springer
98views Algorithms» more  WDAG 2004»
15 years 7 months ago
Dynamic Memory ABP Work-Stealing
The non-blocking work-stealing algorithm of Arora, Blumofe, and Plaxton (hencheforth ABP work-stealing) is on its way to becoming the multiprocessor load balancing technology of ch...
Danny Hendler, Yossi Lev, Nir Shavit