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TPDS
2002
105views more  TPDS 2002»
13 years 6 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
MICRO
2005
IEEE
145views Hardware» more  MICRO 2005»
13 years 12 months ago
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we...
Fred A. Bower, Daniel J. Sorin, Sule Ozev
ICPR
2008
IEEE
14 years 24 days ago
Error-Correcting output coding for chagasic patients characterization
The Chagas’ disease is endemic in all Latin America, affecting millions of people in the continent. In order to diagnose and treat the chagas’ disease, it is important to dete...
Sergio Escalera, Oriol Pujol, Petia Radeva
STOC
2005
ACM
150views Algorithms» more  STOC 2005»
14 years 6 months ago
Correcting errors without leaking partial information
This paper explores what kinds of information two parties must communicate in order to correct errors which occur in a shared secret string W. Any bits they communicate must leak ...
Yevgeniy Dodis, Adam Smith
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
13 years 11 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris