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EH
2003
IEEE
135views Hardware» more  EH 2003»
15 years 5 months ago
Towards Evolvable IP Cores for FPGAs
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
Lukás Sekanina
ICCAD
1996
IEEE
131views Hardware» more  ICCAD 1996»
15 years 3 months ago
Multi-level logic optimization for low power using local logic transformations
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
Qi Wang, Sarma B. K. Vrudhula
IADIS
2004
15 years 1 months ago
SMS transmission using PDU mode and 7-bit coding scheme
This paper describes the design and implementation of an SMS transmission system using the PDU (Protocol Data Unit) mode of a GSM (Global System for Mobile Communications) modem. ...
Andrés Ortiz, Alberto Prieto
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
14 years 3 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
ECCTD
2011
72views more  ECCTD 2011»
13 years 11 months ago
Managing variability for ultimate energy efficiency
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
Borivoje Nikolic