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ETS
2009
IEEE
128views Hardware» more  ETS 2009»
14 years 9 months ago
Algorithms for ADC Multi-site Test with Digital Input Stimulus
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...
Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido...
TE
2010
168views more  TE 2010»
14 years 6 months ago
Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education
The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test educat...
John Hu, Mark Haffner, Samantha Yoder, Mark Scott,...
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
15 years 6 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
VTS
2000
IEEE
167views Hardware» more  VTS 2000»
15 years 4 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
DAC
2005
ACM
15 years 1 months ago
Minimizing peak current via opposite-phase clock tree
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu