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ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
15 years 1 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...
DAC
2007
ACM
16 years 19 days ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
ICCAD
2007
IEEE
111views Hardware» more  ICCAD 2007»
15 years 8 months ago
Exploiting STI stress for performance
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
ICCAD
2004
IEEE
102views Hardware» more  ICCAD 2004»
15 years 8 months ago
True crosstalk aware incremental placement with noise map
Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the rout...
Haoxing Ren, David Zhigang Pan, Paul Villarrubia
SENSYS
2009
ACM
15 years 6 months ago
Low-power clock synchronization using electromagnetic energy radiating from AC power lines
Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cyclin...
Anthony Rowe, Vikram Gupta, Ragunathan Rajkumar