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CADE
2007
Springer
15 years 10 months ago
2007
Springer
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...
ATVA
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. The saturation state-space generation algorithm has demonstrated clear improvements over state-of-the-art symbolic methods for asynchronous systems. This work is motivate...
IFM
2009
Springer
15 years 4 months ago
2009
Springer
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
POLICY
2005
Springer
15 years 3 months ago
2005
Springer
Policy refinement is meant to derive lower-level policies from higher-level ones so that these more specific policies are better suited for use in different execution environments...