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DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
15 years 10 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
ECOWS
2006
Springer
15 years 10 months ago
Verifying Correctness of Web Services Choreography
This paper is about Web services used in distributed, inter-organizational business cooperation (choreography). In this application scenario, we have a multipart functional conven...
Tarek Melliti, Céline Boutrous-Saab, Sylvai...
FORMATS
2006
Springer
15 years 10 months ago
Timed Alternating-Time Temporal Logic
We add freeze quantifiers to the game logic ATL in order to specify real-time objectives for games played on timed structures. We define the semantics of the resulting logic TATL b...
Thomas A. Henzinger, Vinayak S. Prabhu
ACSD
2001
IEEE
134views Hardware» more  ACSD 2001»
15 years 10 months ago
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
We present a new way to define the semantics of imperative synchronous languages by means of separating the control and the data flow. The control flow is defined by predicates th...
Klaus Schneider
186
Voted
FMCAD
2000
Springer
15 years 10 months ago
A Methodology for Large-Scale Hardware Verification
Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities und...
Mark Aagaard, Robert B. Jones, Thomas F. Melham, J...