92 search results - page 4 / 19 » FADIC: Architectural Synthesis applied in IC Design |
LCN
2003
IEEE
15 years 4 months ago
2003
IEEE
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...
306
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DAC
2012
ACM
13 years 2 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
82
Voted
IISWC
2008
IEEE
15 years 6 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
ICCAD
1995
IEEE
15 years 3 months ago
1995
IEEE
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
105
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CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...