27 search results - page 3 / 6 » FDRA: A Software-Pipelining Algorithm for Embedded VLIW Proc... |
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
ISCAS
2007
IEEE
14 years 17 days ago
2007
IEEE
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
LCTRTS
2007
Springer
14 years 12 days ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
CASES
2006
ACM
13 years 10 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
TVLSI
2002
13 years 5 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...