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» FPGA Architecture: Survey and Challenges
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SIGCOMM
2010
ACM
15 years 17 days ago
Caliper: a tool to generate precise and closed-loop traffic
Generating realistic and responsive traffic that reflects different network conditions is a challenging problem associated with performing valid experiments in network testbeds. I...
Monia Ghobadi, Martin Labrecque, Geoffrey Salmon, ...
PERVASIVE
2007
Springer
14 years 12 months ago
Mobiscopes for Human Spaces
The proliferation of affordable mobile devices with processing and sensing capabilities, together with the rapid growth in ubiquitous network connectivity, herald an era of Mobisc...
Tarek F. Abdelzaher, Yaw Anokwa, Péter Boda...
CODES
2008
IEEE
15 years 6 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 5 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
92
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ARC
2009
Springer
134views Hardware» more  ARC 2009»
15 years 5 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...