145 search results - page 4 / 29 » FPGA Design Automation: A Survey |
ASPDAC
2012
ACM
13 years 5 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
TCAD
2008
14 years 9 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
81
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...