This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Over the past half decade, we have been exploring the use of logic in the specification and analysis of computational economic mechanisms. We believe that this approach has the p...
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...