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» FPGA Design Automation: A Survey
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ERSA
2010
186views Hardware» more  ERSA 2010»
14 years 7 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
DSD
2007
IEEE
116views Hardware» more  DSD 2007»
15 years 3 months ago
Evaluating the Model Accuracy in Automated Design Space Exploration
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper...
Kalle Holma, Mikko Setälä, Erno Salminen...
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
15 years 1 months ago
Automatically mapping applications to a self-reconfiguring platform
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...
Karel Bruneel, Fatma Abouelella, Dirk Stroobandt
IPPS
2000
IEEE
15 years 2 months ago
JRoute: A Run-Time Routing API for FPGA Hardware
JRoute is a set of Java classes that provide an application programming interface (API) for routing of Xilinx FPGA devices. The interface allows various levels of control from conn...
Eric Keller
67
Voted
DAC
2008
ACM
15 years 10 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck