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» FPGA Implementations of the Massively Parallel GCA Model
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DAGSTUHL
2007
14 years 11 months ago
Parallelism through Digital Circuit Design
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eļ¬...
John O'Donnell
PADS
2003
ACM
15 years 2 months ago
An Implementation of the SSF Scalable Simulation Framework on the Cray MTA
Large-scale parallel discrete event simulations of massive networks, such as the Internet, are ā€œGrand Challengeā€ problems: packet level simulation of even a small fraction of ...
Robert R. Henry, Simon Kahan, Jason Liu, David M. ...
ARC
2008
Springer
104views Hardware» more  ARC 2008»
14 years 11 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
DAC
2006
ACM
15 years 10 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
ARC
2010
Springer
126views Hardware» more  ARC 2010»
14 years 7 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...