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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
15 years 10 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
CODES
2006
IEEE
15 years 3 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
CODES
2006
IEEE
15 years 3 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst
TIFS
2008
142views more  TIFS 2008»
14 years 9 months ago
An FPGA-Based Network Intrusion Detection Architecture
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...
WER
2004
Springer
15 years 3 months ago
Enhancing Requirements to derive Multi-Agent Architectures
Software systems of today are characterized by the increasing size, complexity, distribution and heterogeneity. Understanding and supporting the interaction between software requir...
Lúcia R. D. Bastos, Jaelson Brelaz de Castr...