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ARC
2010
Springer
178views Hardware» more  ARC 2010»
15 years 4 months ago
An Analysis of Delay Based PUF Implementations on FPGA
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabri...
Sergey Morozov, Abhranil Maiti, Patrick Schaumont
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
15 years 10 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
HICSS
2002
IEEE
123views Biometrics» more  HICSS 2002»
15 years 2 months ago
On the Performance of a Survivability Architecture for Networked Computing Systems
This research focuses on the performance and timing behavior of a two level survivability architecture. The lower level of the architecture involves attack analysis based on kernel...
William S. Harrison, Axel W. Krings, Nadine Hanebu...
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
15 years 2 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 2 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan