353 search results - page 6 / 71 » FPGA architecture characterization for system level performa... |
IEEEPACT
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
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IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
JSA
2010
14 years 4 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
EIT
2008
IEEE
15 years 4 months ago
2008
IEEE
—The rapid growth and pervasive use of embedded systems makes it easier for an adversary to gain physical access to these devices to launch attacks and reverse engineer of the sy...
ERSA
2006
14 years 11 months ago
2006
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...