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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
16 years 2 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
ICPPW
2002
IEEE
15 years 10 months ago
A Statistical Approach for the Analysis of the Relation Between Low-Level Performance Information, the Code, and the Environment
This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design o...
Nayda G. Santiago, Diane T. Rover, Domingo Rodr&ia...
IPPS
2002
IEEE
15 years 10 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
CODES
2005
IEEE
15 years 10 months ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga...
VLSISP
2008
203views more  VLSISP 2008»
15 years 5 months ago
FPGA-based System for Real-Time Video Texture Analysis
This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract 2nd -order statistical features from video frames. These features ...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...