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FPL
2004
Springer
205views Hardware» more  FPL 2004»
15 years 2 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
FPL
2008
Springer
178views Hardware» more  FPL 2008»
14 years 11 months ago
High-speed regular expression matching engine using multi-character NFA
An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which a...
Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kam...
AHS
2006
IEEE
137views Hardware» more  AHS 2006»
15 years 3 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
CHES
2005
Springer
111views Cryptology» more  CHES 2005»
15 years 3 months ago
Hardware Acceleration of the Tate Pairing in Characteristic Three
Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core comp...
Philipp Grabher, Dan Page
FPL
2007
Springer
100views Hardware» more  FPL 2007»
15 years 3 months ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton