134 search results - page 21 / 27 » FPGA implementation of log-polar mapping |
IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reco...
FPL
1997
Springer
15 years 1 months ago
1997
Springer
Abstract. Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency assoc...
ERSA
2008
14 years 11 months ago
2008
This paper presents an accelerator for k-th nearest neighbor thinning, a run time intensive algorithmic kernel used in recent multi-objective optimizers. We discuss the thinning al...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
DATE
2008
IEEE
15 years 3 months ago
2008
IEEE
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...