Sciweavers

134 search results - page 25 / 27
» FPGA implementation of log-polar mapping
Sort
View
APCCAS
2006
IEEE
271views Hardware» more  APCCAS 2006»
15 years 3 months ago
Leakage Optimized DECAP Design for FPGAs
— On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associa...
Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, ...
101
Voted
HOTI
2005
IEEE
15 years 3 months ago
SIFT: Snort Intrusion Filter for TCP
Intrusion rule processing in reconfigurable hardware enables intrusion detection and prevention services to run at multi Gigabit/second rates. High-level intrusion rules mapped d...
Michael Attig, John W. Lockwood
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
15 years 3 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
ISNN
2005
Springer
15 years 3 months ago
A SIMD Neural Network Processor for Image Processing
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
Dongsun Kim, Hyunsik Kim, Hongsik Kim, Gunhee Han,...
ISQED
2002
IEEE
137views Hardware» more  ISQED 2002»
15 years 2 months ago
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson