Sciweavers

134 search results - page 6 / 27
» FPGA implementation of log-polar mapping
Sort
View
ESANN
2006
14 years 11 months ago
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
Benjamin Schrauwen, Jan M. Van Campenhout
FPGA
1995
ACM
93views FPGA» more  FPGA 1995»
15 years 1 months ago
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...
Jason Cong, Yean-Yow Hwang
FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
15 years 1 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 1 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
86
Voted
DSD
2009
IEEE
141views Hardware» more  DSD 2009»
14 years 7 months ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu