87 search results - page 17 / 18 » FPGA power reduction using configurable dual-Vdd |
FCCM
1998
IEEE
13 years 10 months ago
1998
IEEE
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
CGO
2005
IEEE
13 years 12 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...