Sciweavers

1862 search results - page 101 / 373
» FPGA
Sort
View
128
Voted
FPL
2007
Springer
98views Hardware» more  FPL 2007»
15 years 5 months ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
138
Voted
DATE
2008
IEEE
130views Hardware» more  DATE 2008»
15 years 5 months ago
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications
This paper presents the implementation of a dualpriority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkern...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
158
Voted
FPL
2010
Springer
210views Hardware» more  FPL 2010»
15 years 1 months ago
A Compact Transactional Memory Multiprocessor System on FPGA
In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPGA) with support for software transactional memory. The system is composed only b...
Matteo Pusceddu, Simone Ceccolini, Gianluca Palerm...
157
Voted
ERSA
2009
387views Hardware» more  ERSA 2009»
15 years 1 months ago
Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices
Abstract-- The paper presents the implementation of nonlinear least-squares regression in a Field Programmable Gate Array (FPGA) device. The implemented algorithm is very performan...
Andrea Abba, Antonio Manenti, Andrea Suardi, Angel...
124
Voted
DAC
2002
ACM
16 years 4 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...