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ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
16 years 27 days ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
ARC
2009
Springer
165views Hardware» more  ARC 2009»
15 years 10 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont
CASES
2009
ACM
15 years 10 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
SAMOS
2007
Springer
15 years 10 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
15 years 10 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...