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FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 9 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
FPL
2004
Springer
103views Hardware» more  FPL 2004»
15 years 9 months ago
JHDLBits: The Merging of Two Worlds
Abstract. This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits wi...
Alexandra Poetter, Jesse Hunter, Cameron Patterson...
FCCM
2003
IEEE
185views VLSI» more  FCCM 2003»
15 years 9 months ago
Implementation of a Content-Scanning Module for an Internet Firewall
A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing ope...
James Moscola, John W. Lockwood, Ronald Prescott L...
166
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FCCM
2003
IEEE
210views VLSI» more  FCCM 2003»
15 years 9 months ago
Compact FPGA-based True and Pseudo Random Number Generators
Two FPGA based implementations of random number generators intended for embedded cryptographic applications are presented. The first is a true random number generator (TRNG) whic...
Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong
ICES
2003
Springer
93views Hardware» more  ICES 2003»
15 years 9 months ago
A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMar...