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FCCM
2002
IEEE
208views VLSI» more  FCCM 2002»
15 years 9 months ago
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
Nicholas Weaver, John Wawrzynek
FPL
2009
Springer
85views Hardware» more  FPL 2009»
15 years 8 months ago
Generating high-performance custom floating-point pipelines
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...
Florent de Dinechin, Cristian Klein, Bogdan Pasca
FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 7 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
136
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ERSA
2007
174views Hardware» more  ERSA 2007»
15 years 5 months ago
High-Level Specification of Runtime Reconfigurable Designs
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
Stephen D. Craven, Peter M. Athanas
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
15 years 2 months ago
A PUF design for secure FPGA-based embedded systems
The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counterpiracy...
Jason Helge Anderson