1862 search results - page 135 / 373 » FPGA |
109
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DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
16 years 5 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
111
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DAC
2005
ACM
16 years 5 months ago
2005
ACM
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
121
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DAC
2006
ACM
16 years 5 months ago
2006
ACM
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
140
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VLSID
2006
IEEE
16 years 4 months ago
2006
IEEE
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
