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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
16 years 28 days ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
ARC
2009
Springer
111views Hardware» more  ARC 2009»
15 years 10 months ago
A Protocol for Secure Remote Updates of FPGA Configurations
Saar Drimer, Markus G. Kuhn
RECONFIG
2009
IEEE
172views VLSI» more  RECONFIG 2009»
15 years 10 months ago
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
Shivam Bhasin, Jean-Luc Danger, Florent Flament, T...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
— Multiprocessors on a chip are the reality of these days. Semiconductor industry has recognized this approach as the most efficient in order to exploit chip resources, but the ...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
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DATE
2008
IEEE
90views Hardware» more  DATE 2008»
15 years 10 months ago
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System
Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph ...