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    IPPS
    2006
    IEEE
    258views Distributed And Parallel Com...» more  IPPS 2006»
    VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow
    15 years 10 months ago
    VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow
    Download  www.cecs.uci.edu
    Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenz...
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    IPPS
    2006
    IEEE
    107views Distributed And Parallel Com...» more  IPPS 2006»
    FPGA based architecture for DNA sequence comparison and database search
    15 years 10 months ago
    FPGA based architecture for DNA sequence comparison and database search
    Download  f21.aaa.livedoor.jp
    DNA sequence comparison is a computationally intensive problem, known widely since the competition for human DNA decryption. Database search for DNA sequence comparison is of grea...
    Euripides Sotiriades, Christos Kozanitis, Apostolo...
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    IPPS
    2006
    IEEE
    100views Distributed And Parallel Com...» more  IPPS 2006»
    Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
    15 years 10 months ago
    Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
    Download  www.cecs.uci.edu
    Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
    Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
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    IPPS
    2006
    IEEE
    99views Distributed And Parallel Com...» more  IPPS 2006»
    Performance of FPGA implementation of bit-split architecture for intrusion detection systems
    15 years 10 months ago
    Performance of FPGA implementation of bit-split architecture for intrusion detection systems
    Download  halcyon.usc.edu
    Hong-Jip Jung, Zachary K. Baker, Viktor K. Prasann...
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    ISCAS
    2006
    IEEE
    109views Hardware» more  ISCAS 2006»
    A bit-serial approximate min-sum LDPC decoder and FPGA implementation
    15 years 10 months ago
    A bit-serial approximate min-sum LDPC decoder and FPGA implementation
    Download  www.eecg.toronto.edu
    Ahmad Darabiha, Anthony Chan Carusone, Frank R. Ks...
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