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DAC
2000
ACM
16 years 5 months ago
An architecture-driven metric for simultaneous placement and global routing for FPGAs
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
Yao-Wen Chang, Yu-Tsang Chang
VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
16 years 4 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
16 years 1 months ago
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor
This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We ...
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, ...
ICCAD
2004
IEEE
95views Hardware» more  ICCAD 2004»
16 years 1 months ago
Low-power programmable routing circuitry for FPGAs
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...
Jason Helge Anderson, Farid N. Najm
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 1 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen