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FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
15 years 3 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
93
Voted
FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
15 years 1 months ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
85
Voted
DAC
2003
ACM
15 years 10 months ago
Timing optimization of FPGA placements by logic replication
Giancarlo Beraudo, John Lillis
ASPDAC
2009
ACM
255views Hardware» more  ASPDAC 2009»
15 years 4 months ago
A low-power FPGA based on autonomous fine-grain power-gating
— This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell e...
Shota Ishihara, Masanori Hariyama, Michitaka Kamey...
FPL
2003
Springer
144views Hardware» more  FPL 2003»
15 years 2 months ago
FPGA Implementations of Neural Networks - A Survey of a Decade of Progress
The first successful FPGA implementation [1] of artificial neural networks (ANNs) was published a little over a decade ago. It is timely to review the progress that has been made i...
Jihan Zhu, Peter Sutton