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ERSA
2003
147views Hardware» more  ERSA 2003»
15 years 5 months ago
Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications
Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an applicati...
Timothy F. Oliver, Douglas L. Maskell
ARC
2010
Springer
183views Hardware» more  ARC 2010»
15 years 4 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
TCAD
2008
116views more  TCAD 2008»
15 years 4 months ago
Scalable Synthesis and Clustering Techniques Using Decision Diagrams
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
TVLSI
2008
111views more  TVLSI 2008»
15 years 4 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
FPL
2010
Springer
170views Hardware» more  FPL 2010»
15 years 2 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...