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FPGA
1997
ACM
118views FPGA» more  FPGA 1997»
15 years 8 months ago
Module Generation of Complex Macros for Logic-Emulation Applications
Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design veri cation. Using an emulator, designers can realize designs through a soft...
Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
FPGA
2006
ACM
195views FPGA» more  FPGA 2006»
15 years 8 months ago
An adaptive Reed-Solomon errors-and-erasures decoder
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Rus...
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 4 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
16 years 1 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 9 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew