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IOLTS
2000
IEEE
84views Hardware» more  IOLTS 2000»
15 years 2 months ago
Self-Testing of FPGA Delay Faults in the System Environment
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
Andrzej Krasniewski
FPGA
1998
ACM
180views FPGA» more  FPGA 1998»
15 years 1 months ago
A Novel Predictable Segmented FPGA Routing Architecture
Emil S. Ochotta, Patrick J. Crotty, Charles R. Eri...
FTEDA
2006
208views more  FTEDA 2006»
14 years 9 months ago
FPGA Design Automation: A Survey
Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA technology ove...
Deming Chen, Jason Cong, Peichen Pan
ICES
2005
Springer
195views Hardware» more  ICES 2005»
15 years 3 months ago
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs
A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on t...
Jan Korenek, Lukás Sekanina
DAC
2008
ACM
15 years 10 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...