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PDPTA
2000
15 years 5 months ago
Constant Multipliers for FPGAs
This paper presents a survey of techniques to implement multiplications by constants on FPGAs. It shows in particular that a simple and well-known technique, canonical signed recod...
Florent de Dinechin, Vincent Lefèvre
TCAD
2008
112views more  TCAD 2008»
15 years 4 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
FPL
2010
Springer
155views Hardware» more  FPL 2010»
15 years 2 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
DSD
2009
IEEE
141views Hardware» more  DSD 2009»
15 years 2 months ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu
VLSISP
2010
119views more  VLSISP 2010»
14 years 11 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton