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JSA
2002
130views more  JSA 2002»
15 years 5 months ago
Reconfigurable models of finite state machines and their implementation in FPGAs
This paper examines some models of FSMs that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a wa...
Valery Sklyarov
TVLSI
2002
116views more  TVLSI 2002»
15 years 5 months ago
Configuration relocation and defragmentation for run-time reconfigurable computing
Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. By mapping the compute-intens...
Katherine Compton, Zhiyuan Li, James Cooley, Steph...
CORR
2010
Springer
159views Education» more  CORR 2010»
15 years 5 months ago
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
Bin Wu, Guido Masera
INTEGRATION
2008
127views more  INTEGRATION 2008»
15 years 4 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
VLSISP
2008
103views more  VLSISP 2008»
15 years 3 months ago
Power Signature Watermarking of IP Cores for FPGAs
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...
Daniel Ziener, Jürgen Teich