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PAIRING
2010
Springer
153views Cryptology» more  PAIRING 2010»
15 years 3 months ago
Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves
This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such cu...
Nicolas Estibals
TPDS
2010
260views more  TPDS 2010»
15 years 3 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear
ASPDAC
2010
ACM
183views Hardware» more  ASPDAC 2010»
15 years 3 months ago
Multi-operand adder synthesis on FPGAs using generalized parallel counters
Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
199
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CSREAESA
2010
15 years 3 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
ERSA
2010
199views Hardware» more  ERSA 2010»
15 years 3 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot