1862 search results - page 239 / 373 » FPGA |
165
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ICES
2003
Springer
15 years 10 months ago
2003
Springer
This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...
145
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GLVLSI
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
135
Voted
ISSS
2002
IEEE
15 years 10 months ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
112
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FPL
2009
Springer
15 years 10 months ago
2009
Springer
Power consumption in data centres is a growing issue as the cost of the power for computation and cooling has become dominant. An emerging challenge is the development of “envir...
122
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FPL
2009
Springer
15 years 10 months ago
2009
Springer
Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual μP...