1862 search results - page 251 / 373 » FPGA |
157
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ICC
2009
IEEE
16 years 7 hour ago
2009
IEEE
—This paper presents the field-programmable gate array (FPGA) implementation of a variant of the LenstraLenstra-Lov´asz (LLL) lattice reduction (LR) algorithm, known as the Cla...
146
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RECONFIG
2009
IEEE
15 years 12 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
152
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IROS
2009
IEEE
15 years 12 months ago
2009
IEEE
— In this paper, we introduce a high-speed vision platform, H3 (Hiroshima Hyper Human) Vision, which can simultaneously process a 1024× 1024 pixel image at 1000 fps and a 256× ...
165
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ASAP
2008
IEEE
15 years 11 months ago
2008
IEEE
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant s...
112
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DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose lin...