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ISCAS
2008
IEEE
127views Hardware» more  ISCAS 2008»
15 years 11 months ago
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection
— ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC imple...
Huiju Cheng, Howard M. Heys
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
15 years 11 months ago
Algorithm for parallel inverse halftoning using partitioning of Look-Up Table (LUT)
— The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to ...
Umair F. Siddiqi, Sadiq M. Sait
RTCSA
2008
IEEE
15 years 11 months ago
Concepts of Switching in the Time-Triggered Network-on-Chip
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
Christian Paukovits, Hermann Kopetz
VTC
2008
IEEE
105views Communications» more  VTC 2008»
15 years 11 months ago
Implementation of Single Carrier Packet Transmission with Frequency Domain Equalization
—Single-carrier (SC) transmission using frequency domain equalization (FDE) is one of the candidates for the next generation mobile communication systems expected to deliver high...
Valentin Gheorghiu, Suguru Kameda, Tadashi Takagi,...
AFRICACRYPT
2008
Springer
15 years 11 months ago
Implementation of the AES-128 on Virtex-5 FPGAs
Abstract. This paper presents an updated implementation of the Advanced Encryption Standard (AES) on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in th...
Philippe Bulens, François-Xavier Standaert,...