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CHES
2005
Springer
111views Cryptology» more  CHES 2005»
15 years 10 months ago
Hardware Acceleration of the Tate Pairing in Characteristic Three
Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core comp...
Philipp Grabher, Dan Page
FPL
2005
Springer
127views Hardware» more  FPL 2005»
15 years 10 months ago
Efficient Hardware Architectures for Modular Multiplication on FPGAs
The computational fundament of most public-key cryptosystems is the modular multiplication. Improving the efficiency of the modular multiplication is directly associated with the...
David Narh Amanor, Viktor Bunimov, Christof Paar, ...
FPL
2005
Springer
89views Hardware» more  FPL 2005»
15 years 10 months ago
Snow 2.0 IP Core for Trusted Hardware
Stream ciphers are a promising technique for encryption in trusted hardware. ISO/IEC standardization is currently under way and SNOW 2.0 is one of the remaining candidates. Its sof...
Wenhai Fang, Thomas Johansson, Lambert Spaanenburg
112
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FPL
2005
Springer
100views Hardware» more  FPL 2005»
15 years 10 months ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
FPL
2005
Springer
125views Hardware» more  FPL 2005»
15 years 10 months ago
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...