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FPL
2005
Springer
114views Hardware» more  FPL 2005»
15 years 10 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
FPL
2005
Springer
107views Hardware» more  FPL 2005»
15 years 10 months ago
Programmable Numerical Function Generators: Architectures and Synthesis Method
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
FPL
2005
Springer
100views Hardware» more  FPL 2005»
15 years 10 months ago
Power and Area Optimization for Multiple Restricted Multiplication
This paper presents a design and optimization technique for the Multiple Restricted Multiplication problem [1]. This refers to a situation where a single variable is multiplied by...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
FPL
2005
Springer
138views Hardware» more  FPL 2005»
15 years 10 months ago
Snort Offloader: A Reconfigurable Hardware NIDS Filter
Software-based Network Intrusion Detection Systems (NIDS) often fail to keep up with high-speed network links. In this paper an FPGA-based pre-filter is presented that reduces th...
Haoyu Song, Todd S. Sproull, Michael Attig, John W...
ICARIS
2005
Springer
15 years 10 months ago
A Generic Framework for Population-Based Algorithms, Implemented on Multiple FPGAs
Many bio-inspired algorithms (evolutionary algorithms, artificial immune systems, particle swarm optimisation, ant colony optimisation, …) are based on populations of agents. Ste...
John Newborough, Susan Stepney